The invention relates to a filter circuit consisting of at least one filter stage in which amplifier-like circuits such as integrators and/or gyrators are employed to emulate the impedance of inductors. The invention also relates to a method for making (designing) such filter circuit.
The invention in particular addresses the problem how complex (higher order) filters can be designed such that the actual filter characteristics obtained in the practically realized filter circuit coincide with the theoretically designed filter characteristics. The invention also addresses the problem how such complex (e.g. higher order) filters can be designed such that they are stable.
As shown in FIG. 1, typically a filter circuit consists of a plurality of filter stages FST1 . . . FSTi wherein the first filter stage FST1 is driven by a source, e.g. a current source CS and a source impedance SI, and the output of the last filter stage FSTi is terminated with an output impedance OI. As is well known to the skilled person the filter transfer function is essentially a polynomial consisting of a plurality of poles and zeros in the complex plane. Depending as to whether the individual filter stages FSTi are a filter stage of first order or higher order, a desired filter function and thus a desired filter characteristic can be obtained.
Hereinafter, it is assumed that each filter stage FSTi consists of a single transistor or gyrator. However, of course the invention is not restricted to each filter stage being of the said types but also higher order filter stages may be used.
Depending on the desired filter transfer function, each filter stage is realized by coils, resistors and capacitors. For example, on-chip filters are normally restricted to resistor/capacitor filter stages, except at very high frequencies where on-chip coils of a few nH may be employed. In such passive filter realizations (i.e. no active circuitry is employed in the filter stages FSTi) it therefore depends on how accurate or whether at all coils (more particular the coil impedance) can be realized by a passive coil construction.
As is also well known to the skilled person in the art of filter design, active on-chip filters are often used to circumvent the coil restrictions in passive filter circuits. In such active filters amplifier-like circuitry is used to emulate the impedance of the inductors. That is, the coils are replaced by an active circuit. For continuous-time filters such amplifier-like circuits typically consist of integrators or gyrators and for discrete-time circuits (digital filters) integrators are used for emulating the coils impedance.
Continuous-time filters implemented with integrators typically employ such elements in loops and these loops. Two integrators in a loop actually form a gyrator. If the forward and backward integrators have the same gain characteristics they form a passive gyrator and if they do not have the same gain characteristics they form an active (or asymmetric) gyrator. FIG. 2 shows a typical block diagram of a gyrator and its equivalent circuit diagram. The input voltage V1 and the output voltage V2 are linked via the gyration constant gm* as I1=xe2x88x92gm*V2 and I2=gm*V1. Thus, the gyrator shown in FIG. 2 consists of a positive transconductance gm* and a negative transconductance xe2x88x92gm*.
FIG. 3 shows a typical realization of the gyrator in FIG. 2 employing at least one common mode feedback section CMIi, CMOi and a gyrator core section GCi. As shown in FIG. 3, the negative transconductance xe2x88x92gm* is typically formed by employing differential signals and crossing one pair of wires. That is, the gyrator core section GCi comprises four inverters GI1i-GI4i mutually connected in a loop configuration between a pair of input terminals i_1; i_2 and a pair of output terminals o_1; o_2. The common mode feedback section CMIi, CMOi is connected between the pair of input terminals and/or the pair of output terminals and comprises two series connections respectively formed by an inverter CMI1, CMO1 and a short-circuited inverter CMI2, CMO2 connected antiparallely between said input terminals or said output terminals. It should be noted that one of the input or output common mode feedback sections CMIi, CMOi is sufficient for realizing the positive transconductance gm* and that one gyrator core section GCi is sufficient for realizing the negative transconductance xe2x88x92gm.
However, independent as to how the actual inverters are realized (by MOS, CMOS, BiCMOS or bipolar transistors), the crossing of the wires results in a loop through the four inverters GI1i, GI2i, GI3i, GI4i. FIG. 4 shows the realization of the inverters in FIG. 3 using two CMOS transistors T1 (e.g. NMOS) and T2 (e.g. PMOS) whose drains D and gates G are connected with the respective sources connected to ground. Similarly, the short-sectioned inverters would correspond to the circuit configuration shown in FIG. 4 with the input In and the output Out connected together.
Furthermore, gyrators realized by differential amplifier circuitry are possible, as shown in FIGS. 5a, 5b. FIG. 5a shows on the left-hand side the symbol for a transconductor realized by a differential amplifier and on right-hand side the inverter solution for such a differential type amplifier in CMOS technology is shown. Two inverters I1, I2 (e.g. having a circuit configuration as shown in FIG. 4) are respectively connected to a first and second current source CS1, CS2 which are biased by bias voltages bias1, bias2.
FIG. 5b shows the gyrator core section GCi of FIG. 3 using a differential transconductor configuration as in FIG. 5a. As shown on the left-hand side in FIG. 5b two differential transconductors DA1, DA2 are provided in a feedback loop and therefore, using the circuit configuration in FIG. 5a, this leads to a structure similar to that shown in FIG. 3, namely loop-like circuits in the gyrator core section GCi.
In FIG. 5b the circuit configuration of FIG. 5a is contained twice leading to two first current sources CS1, CS12 and to second current sources CS21, CS22, to first inverters I11, I12 and to second inverters I21, I22.
It should be noted that any gyrator configuration as shown in FIGS. 3, 4, 5 may be used for the filter circuit according to the invention as will be described below. That is, the present invention is not restricted to any particular gyrator constructions. However, any gyrator construction would lead to the loop-like circuit of the gyrator core section GCi as shown in FIG. 3. The only difference is that for the differential amplifier gyrator shown in FIG. 5b no common mode feedback is needed because in the differential transconductor a high CMRR (Common Mode Rejection Ratio) exists.
As explained above, the loop-like configuration of the gyrator leads to a stability problem and the stability analysis of the gyrator- and integrator-based filters is the same since the integrators are parts of gyrator loops. An analysis of the gyrators is thus valid for the integrator configuration as well.
The stability of filter circuits comprising a gyrator construction as shown in FIG. 3 has been studied by B. Nauta: xe2x80x9cA CMOS transconductance-C filter technique for very high frequencies in IEEE Journal of Solid-State Circuits, SC-27, pages 142-153, February 1992xe2x80x9d. In this prior art document the stability of the circuit in FIG. 3 (hereinafter called the Nauta cell) was conducted by assuming a MOS or CMOS transistor realization of the integrators in FIG. 3. As is well known to the skilled person in the field of transistor technology, each MOS or CMOS transistor has a channel region of a particular dimension and the time needed for transporting carriers through this channel (between the source and drain) will influence the switching properties of the CMOS or MOS transistor.
In a PhD thesis which is the basis for the afore-mentioned IEEE paper, Nauta presented a number of simple filters and complex intermediate-frequency (IF) filters. The filter structures of lower order did work well but the more complex ones (higher order filters) had a very poor frequency response. In particular, the measured filter characteristics deviated from the theoretically expected filter characteristic to more than 10 dB. Furthermore, stability problems occurred and for making the filter circuits stable a separate Q-tuning circuit (separate supply voltage for the ballast inverters in the common mode feedback network) was used to enable an external adjustment. Basically, the adding of ballast devices or the sizing of the inverters in the common mode feedback sections reduces the dependence of the filter circuit on the output conductance of the filter and thus leads to more stable filter characteristics. Whilst Nauta achieved to make the filter stable by the adding of the Q-tuning circuits, the filter characteristics significantly deviated from the expected behavior. Thus, obviously merely adding ballast inverters in the common mode feedback network is not sufficient to keep stability and achieve the desired filter characteristic. Furthermore, each individual gyrator would require a separate Q-tuning loop.
Lower-order filters comprising Nauta cells do work because the external terminations provide a sufficient loading of the gyrator to make it stable. On the other hand, higher-order filters tend to have internal nodes that do not get sufficient loading to make the filter stable.
Thus, no complex active continuous-time on-chip MOS filter has been successfully fabricated in products due to the unreliability of the gyrator cell in terms of stability and the only workable examples are limited to lower-order filters or cascades of low-order filters (with inferior sensitivity characteristics).
Therefore, as explained above, the object of the present invention is to provide a filter circuit comprising at least one filter stage including at least one gyrator and a method for making such a filter circuit such that the filter circuit is stable also when higher-order filter stages are used and such that the practically obtained filter characteristic matches the theoretically expected filter characteristic.
This object is solved by the filter circuit (claim 11) consisting of at least one filter stage which comprises: a gyrator core section having four inverters mutually connected in a loop configuration between a pair of input terminals and a pair of output terminals; at least one common mode feedback section connected between the pair of input terminals and/or the pair of output terminals and comprising two series connections respectively formed by an inverter and a short-sectioned inverter connected antiparallely between said input terminals or said output terminals; each of said inverters being constituted by at least one MOS, CMOS or BiCMOS transistor having a gate, drain, source and a channel region between said drain and source; wherein the channel region dimensions of the transistors of the gyrator core section and/or the common mode feedback section are selected such that the following relationship is fulfilled: g*Cxe2x89xa7gm*cm where:
g: effective conductive loading of the gyrator core section terminals; C: effective capacitive loading of the gyrator core section terminals; gm: effective gyrating constant of the gyrator core section; and cm: effective transcapacitance of the gyrator core section.
Furthermore, this object is also solved by a method (claim 1) for making a filter circuit consisting of at least one filter stage which comprises the following steps:
providing said at least one filter stage with a gyrator core section having four inverters mutually connected in a loop configuration between a pair of input terminals and a pair of output terminals; and providing at least one common mode feedback section connected between the pair of input terminals and/or the pair of output terminals and comprising two series connections respectively formed by an inverter and a short-sectioned inverter connected antiparallely between said input terminals or said output terminals; each of said inverters being constituted by at least one MOS, CMOS or BiCMOS transistor having a gate, drain, source and a channel region between said drain and source; including the following step: selecting the channel region dimensions of the transistors of the gyrator core section and/or the common mode feedback section such that the following relationship is fulfilled:
g*Cxe2x89xa7gm*cm where: g: effective conductive loading of the gyrator core section terminals; C: effective capacitive loading of the gyrator core section terminals; gm: effective gyrating constant of the gyrator core section; and cm: effective transcapacitance of the gyrator core section.
Furthermore, the object is solved by a method for making a filter circuit consisting of at least one filter stage FSTi which comprises the following steps:
providing S1 said at least one filter stage FSTi with a gyrator core section GCi having four inverters I1, I12, I22, I21 mutually connected in a feedback loop between a pair of input terminals i_1, i_2 and a pair of output terminals o_1, o_2; wherein the inverters are arranged as a differential transconductor configuration, such that a first and second inverter I11, I21 are respectively provided between the first input and first output terminal i_1; o_2 and the second input terminal and the second output terminal i_2; o_2; each of said inverters being constituted by at least one MOS, CMOS or BiCMOS transistor having a gate G, drain D, source S and a channel region CH between said drain D and source S;
selecting S4 the general region dimensions CL, CB of the transistors of the gyrator core section such that the following relationship is fulfilled: g*Cxe2x89xa7gm*cm 
where: g: effective conductive loading of the gyrator core section terminals; C: effective capacitive loading of the gyrator core section terminals; gm: effective gyrating constant of the gyrator core section; and cm: effective transcapacitance of the gyrator core section.
Furthermore, this object is solved by a filter circuit consisting of at least one filter stage FSTi, which comprises:
at least one filter stage FSTi with a gyrator core section GCi having four inverters I1, I12, I22, I21 mutually connected in a feedback loop between a pair of input terminals i_1; i_2 and a pair of output terminals o_1; o_2; wherein the inverters are arranged as a differential transconductor configuration, such that a first and second inverter I11, I21 are respectively provided between the first input and first output terminal i_1; o_1 and the second input terminal and the second output terminal i_2; o_2; each of said inverters being constituted by at least one MOS, CMOS or BiCMOS transistor having a gate G, drain D, source S and a channel region CH between said drain D and source S; the general region dimensions CL, CB of the transistors of the gyrator core section being selected such that the following relationship is fulfilled: g*Cxe2x89xa7gm*cm 
where: g: effective conductive loading of the gyrator core section terminals; C: effective capacitive loading of the gyrator core section terminals; gm: effective gyrating constant of the gyrator core section; and cm: effective transcapacitance of the gyrator core section. According to the invention the problem was discovered that the channel delay of the transistor structures used in the gyrator circuits actually make the circuit unstable and causes the deviation from the actual filter characteristic from the expected theoretical filter characteristic. According to the invention it was realized that the non-quasi-static behavior of the channel charge does indeed add a parasitic pole in the transconductance of the device. This extra pole or delay makes the gyrator unstable and therefore must be designed properly. Whenever the channel delay becomes significant, it is therefore necessary to design the channel region dimension such that g*Cxe2x89xa7gm*cm is fulfilled. It is also not necessary to add Q-tuning to the ballast inverters in the common mode feedback network. If the channel region dimensions of the MOS transistors are designed to fulfill this condition also higher-order filters with excellent filter characteristics can be provided.
According to a first aspect of the invention the channel region dimensions are changed differently in the gyrator core section and in said common mode feedback section. The channel region dimensions of the common mode feedback section transistors can be kept constant and the channel region length of the gyrator core section can be reduced whereby the transadmittance of the respective transistor is changed. Thus, the devices are shortened such that the open-circuit voltage gain of the devices is low enough not to cause instability.
According to a second aspect of the invention the channel region dimensions of the common mode feedback section transistors are kept constant and the channel region length and the channel region width of the gyrator core section is reduced wherein the transmittance of the respective transistor is kept constant such that the resonance frequency of the core section {overscore (xcfx89)}Tcore is larger than the resonance frequency of the filter circuit {overscore (xcfx89)}Ofilter. Therefore, the gyrator-core devices can be scaled down such that their delay becomes insignificant.
According to a third aspect of the invention, when the channel region dimensions have been designed such that the overall filter fulfills g*Cxe2x89xa7gm*cm, additional ballast inverters can be added to the common mode feedback section. Essentially, the channel region width of the transistors of the common mode ballast inverters in the common mode feedback section is increased. That is, the CM ballast inverter channel region is widened and one must discriminate here between the CM ballast inverter connected to one terminal (CMI2 and CMO2) whose width is actually increased and the CM inverters connected between terminals (CMI1, CMO1) whose width can be kept constant.
Preferably, the channel length of the CM inverters (CMI1 and/or CMO1) can be made longer (even though this may be inferior to widening CMx2) as this will create a similar gain imbalance.
According to a fourth aspect of the invention, the aforementioned stability criteria and further stability criteria discussed hereinafter can be employed for a filter circuit which is formed by a differential transconductor configuration in a feedback loop without additional common mode feedback sections.
The above-mentioned schemes are applicable to symmetrical and asymmetrical realizations of the inverters.
Further advantageous embodiments and improvements of the invention can be taken from the dependent claims. Furthermore, it should be noted that the invention is not restricted to the embodiments and examples described hereinafter and that further embodiments of the invention may comprise features which have been described separately in the claims and in the description. Hereinafter, embodiments of the invention will be described with reference to the drawings.